Free browser-based control system simulator with block diagrams, PID tuning, transfer functions, state-space models, step response and Bode analysis. No account or installation required.
Engineering reference
The interactive workspace is paired with its published engineering context: core equations, assumptions, design boundaries, and source references. Worked examples, validation cases, and editorial review dates are displayed only where that supporting evidence has been published for the tool.
The simulator is a focused browser-based block-diagram environment for control-system learning and preliminary design. Add source, controller, plant, nonlinear, and scope blocks; wire them together; then simulate the complete closed loop instead of evaluating each equation in isolation.
It is free to use, requires no account or installation, and performs its interactive calculations in the browser. That makes it suitable for quick coursework, demonstrations, and control experiments on a shared or temporary computer.
Phase 2 UX is complete with a viewport-responsive diagram canvas, anchored zoom, Space/middle-mouse panning, fit-to-diagram, box and multi-selection, grouped block dragging, searchable drag-and-drop blocks, direct port wiring and drag-to-rewire, selectable/deletable wires, snap-to-grid, alignment/distribution tools, copy/paste/duplicate, and undo/redo history.
Included templates cover continuous PID/PI tracking, disturbance rejection, transfer functions, state-space plants, delay/noise and rate limits, plus Phase 3 sampled-data examples with digital PID, zero-order hold, discrete G(z), difference equations, discrete state space, and one-sample computation delay. Every template remains fully editable.
Scopes can be assigned as Reference, Output, Error, Control effort, or Auxiliary. When Reference and Output scopes exist, the simulator automatically calculates rise time, peak time, overshoot, settling time, steady-state error, IAE, ISE, ITAE, and ITSE.
The selected continuous or discrete PID block can be adjusted with live tuning sliders, ±10% gain nudges, optional auto-run, one-click rerun, gain revert, or numerical optimization. The first tuning change can preserve the current response as a baseline. Results use a sticky tabbed dock for overview, response, control, error, auxiliary, and linear analysis; time-domain scopes support cursor readouts, drag-to-zoom, Ctrl+wheel zoom, and synchronized time-window reset. Continuous linear-compatible feedback diagrams also derive closed-loop poles, reference-to-output frequency response, open-loop Bode response, bandwidth, gain margin, and phase margin.
A controller cannot be judged from Kp, Ki, and Kd alone. The reference, summing junction, controller, actuator limits, plant dynamics, sensor path, disturbances, delays, and sample timing all shape the closed-loop response.
The block-diagram simulator therefore evaluates connected systems as one dynamic model and reports both tracking performance and controller effort where the necessary scopes are present.
Continuous states are propagated with fixed-step RK4. Digital blocks update only at configured sample instants and hold their outputs between updates, which makes sample time part of the control design rather than a UI setting.
The base step must be small enough to resolve the fastest dynamics and, for the current mixed solver, digital sample times must align with integer multiples of that base step.
Step response exposes rise time, overshoot, settling, steady-state error, integral error, and actuator demand. Bode response, poles, gain margin, and phase margin describe small-signal linear behavior around the modeled operating point.
When nonlinear, delay, noise, or sampled-data blocks make the continuous linear interpretation invalid, the simulator disables the corresponding classical analysis instead of presenting a misleading margin.
Connected sources, summing junctions, controllers, plants, nonlinearities, delays, sensors, and scopes define the simulated system.
Total time window used for the time-domain run.
Fixed RK4 integration step and timing grid used by the mixed continuous/discrete solver.
Reduce the step when the result changes noticeably with step size or when fast dynamics are present.Continuous or discrete PID/PI/P parameters, derivative filtering, saturation, and anti-windup settings.
Transfer-function, state-space, first-order, second-order, or discrete model coefficients.
Update period for digital controllers and discrete dynamic blocks.
Reference, output, error, control effort, and auxiliary scope signals.
Rise time, peak time, overshoot, settling time, and steady-state error where reference/output scopes permit them.
IAE, ISE, ITAE, and ITSE for comparing tracking behavior over the selected run.
Closed-loop poles, Bode response, bandwidth, gain margin, and phase margin for supported continuous linear diagrams.
Baseline-versus-current response metrics and traces for interactive tuning or numerical optimization.
continuous simulation: ẋ=f(x,u,t), integrated with fourth-order Runge–Kutta (RK4)first-order plant: τẏ + y = Kusecond-order plant: ÿ + 2ζωₙẏ + ωₙ²y = Kωₙ²uPID with filtered derivative: u=Kp e + Ki∫e dt + Kd N(e−xD), ẋD=N(e−xD)strictly proper transfer functions are converted to controllable companion-form state space before integrationstate-space plant: ẋ=Ax+Bu, y=Cx+Dudiscrete PID: controller updates at Ts and holds u[k] between sample instantszero-order hold: y(t)=u[k] for kTs≤t<(k+1)Tsunit delay: y[k]=u[k−1]discrete transfer function: a₀y[k]+a₁y[k−1]+…=b₀u[k]+b₁u[k−1]+…difference equation: y[k]=Σbᵢu[k−i]+Σcⱼy[k−j−1]discrete state space: x[k+1]=Ax[k]+Bu[k], y[k]=Cx[k]+Du[k]transport delay: y(t)=u(t−T), using fixed-step history interpolationfrequency response: H(jω)=C(jωI−A)⁻¹B+DIAE=∫|e|dt, ISE=∫e²dt, ITAE=∫t|e|dt, ITSE=∫te²dtUse a first-order plant with K = 1 and τ = 1 s, driven by a unit step without feedback nonlinearities.
Result: The expected output at t = 1 s is approximately 0.6321.
Interpretation: This is a useful sanity check for integration accuracy and for understanding the physical meaning of a first-order time constant.
A fixed-step solver can miss fast dynamics or distort stability when the integration step is large relative to the fastest modeled time constant or sample period.
Better approach: Reduce the base step and confirm that the important metrics and traces converge rather than trusting one discretization.
Aggressive gains can look acceptable in an unconstrained model but demand impossible control effort in the real system.
Better approach: Include saturation, rate limits, delay, sensor behavior, and realistic actuator authority before treating a tuning result as implementable.
Classical continuous margins are not automatically meaningful when dead zones, rate limits, delays, noise models, or digital timing dominate the system.
Better approach: Use the time-domain sampled response for those cases and dedicated z-domain/nonlinear methods when required.
The runtime converts supported continuous dynamic blocks into state derivatives, evaluates the connected diagram, and advances continuous states with classical fourth-order Runge–Kutta. Discrete blocks update at their sample events and retain outputs between events.
Performance metrics are derived from the simulated reference/output/error signals after a run. Linear analysis is constructed only when the diagram can be represented as the supported continuous small-signal model; otherwise it is explicitly withheld.
These checks document how representative calculations are cross-checked against analytic or reference results.
Primary sources are preferred for ratings, standards, manufacturer data, and externally defined constants.