Bench power supply
Output voltage
- Current limit
- —
- Mode check
- CV expected
Virtual engineering lab
RC Time-Constant Measurement
Use the virtual bench supply, DMM, and oscilloscope workflow to measure a first-order RC charging transient and compare the measured 63.2% crossing with τ = RC.
Electrical Engineering / InstrumentationintroductoryValidated educational model
0% complete0 / 0 requirements
Complete the procedure, collect the required measurements, pass the engineering validation, and answer every graded concept question correctly.
What you should establish
- Predict an RC time constant from resistance and capacitance.
- Verify that capacitor voltage reaches 63.2% of its final value at one time constant.
- Check that the bench-supply current limit will not disturb the ideal charging transient.
- Use the DMM resistance reading as an independent component check.
- Compare oscilloscope-derived and analytic time constants.
Work through the experiment
Collect evidence from the model
- Analytic time constantRC time constant calculated directly from component values.Pending
- Scope-measured time constantInterpolated 63.2% crossing from the sampled capacitor-voltage waveform.Pending
- Final capacitor voltageIdeal steady-state capacitor voltage.Pending
- Initial charging currentMaximum ideal current immediately after the step is applied.Pending
- DMM resistance checkIndependent ideal DMM resistance reading before energizing the network.Pending
- Current-limit marginBench-supply current limit minus initial charging current.Pending
Verify the result, not just the workflow
- RC time-constant checkCompares the oscilloscope-style sampled 63.2% crossing against τ = RC.Pending
Only a passed engineering check satisfies guided completion. Warnings and failures remain visible even if the procedure checklist is complete.
Answer the graded multiple-choice questions
Choose one answer for each question. Each selection is graded immediately and saved locally. Guided Lab completion requires every concept question to be correct.
Concept score: 0 / 3 correct
Integrated virtual bench
Ideal instrumentsRC transient bench
Resistance check
COM + VΩ · circuit unpowered
Confirm the modeled series resistance before applying the source.
Oscilloscope
—Transient response
Adjust experiment parameters to preview the ideal response, then run the experiment for validation.
Series R–C network
- Analytic τ
- —
- 63.2% measurement
- —
- Current-limit margin
- —
Measurements
Instrument readings
- Analytic time constant
- — RC time constant calculated directly from component values.
- Scope-measured time constant
- — Interpolated 63.2% crossing from the sampled capacitor-voltage waveform.
- Final capacitor voltage
- — Ideal steady-state capacitor voltage.
- Initial charging current
- — Maximum ideal current immediately after the step is applied.
- DMM resistance check
- — Independent ideal DMM resistance reading before energizing the network.
- Current-limit margin
- — Bench-supply current limit minus initial charging current.
Result visualization
Transient measurement check
Compare the analytic first-order time constant with the oscilloscope-style 63.2% crossing and verify the source current-limit margin.
- Analytic τ
- —
- Measured τ
- —
- Initial current
- —
- Current-limit margin
- —
Independent check: VC(τ) = 0.6321 VS and I(0+) = VS/R.
Theory
Equations and model
First-order capacitor charging
After an ideal DC step is applied through a resistor, capacitor voltage rises exponentially toward the source voltage.
τ = RCVC(t) = VS(1 − e^(−t/RC))VC(τ) = 0.6321 VSSupply-current check
At the instant the step is applied, the uncharged capacitor behaves like a short circuit in the ideal model. The largest charging current is therefore VS/R. If the bench supply enters current limit, the waveform is no longer the simple ideal RC exponential used for this measurement.
I(0+) = VS/RIlimit > I(0+) for this ideal labValidation
Independent checks
RC time-constant checkNot run
Compares the oscilloscope-style sampled 63.2% crossing against τ = RC.
- Expected
- —
- Simulated
- —
- Error
- —
- Tolerance
- 0.25%
Run the experiment to perform this check.
Engineering interpretation
Run the experiment to generate an engineering interpretation.
Assumptions and limitations
Assumptions
- Ideal resistor and capacitor.
- Ideal step source provided the current limit is not reached.
- Infinite oscilloscope input impedance and ideal DMM resistance measurement.
- No ESR, leakage, dielectric absorption, wiring inductance, or source impedance.
Limitations
- Current-limited charging is detected and rejected rather than modeled in Phase 1.6.
- Phase 1.7 demonstrates component tolerance, calibration offset, noise, and quantization in the shared error model; this RC fundamentals run remains ideal so the 63.2% analytic check stays isolated. Probe loading remains a future hardware-specific effect.
Local experiment export
Phase 1.9Save your measurements and setup
Exports are generated in your browser. No account or server upload is required.
- Settings JSON
- Current parameter values for reproducibility and later project handoff.
- Measurements CSV
- Completed instrument readings with labels, units, and descriptions.
- Plot PNG
- The current canvas-based scope, transient, sweep, or statistics visualization when available.
- Summary
- Markdown report with objectives, setup, measurements, validation, interpretation, assumptions, and graded guided concept-check results.
Ready to export the current local experiment state.
What this experiment should establish
- Predict an RC time constant from resistance and capacitance.
- Verify that capacitor voltage reaches 63.2% of its final value at one time constant.
- Check that the bench-supply current limit will not disturb the ideal charging transient.
- Use the DMM resistance reading as an independent component check.
- Compare oscilloscope-derived and analytic time constants.
Questions to answer from the experiment
- Approximately what percentage of final voltage has the capacitor reached after five time constants?
- How would a bench supply entering current-limit mode change the early part of the charging waveform?
- What happens to τ if resistance doubles while capacitance remains fixed?